1. Field of The Invention
The present invention relates to a semiconductor device and a method for designing the semiconductor device, and, in particular, relates to a semiconductor device provided by employing a planarization with silica for an interlayer film and a method for designing the semiconductor device.
2. Related Art
In recent circumstances in modern semiconductor devices, number of layers required for composing an interconnect structure is more and more increased for achieving higher density of elements with lower production cost, and new technologies and new materials are proposed for achieving an improved multiple-layered interconnect. Among these new technologies, a typical technology is to achieve a planarization of an interlayer insulating film by employing a silica film produced via a rotation coating process (hereinafter referred simply as “silica”). In this technology, an interlayer insulating film such as a plasma oxidization film is deposited, and then, the film is coated with silica to fill depressions created between the interconnects with silica, thereby reducing the unevenness in the surface to provide a flat interlayer film.
In addition to above, a method for planarizing a multiple-layered metallic pad on a semiconductor device is described in Japanese Patent No. 2,970,232.
The present inventors have conducted relevant experiments, and have found the following problems.
FIG. 5 is a schematic plan view of a semiconductor device experimentally produced in the experiment.
A semiconductor device shown in FIG. 5 is formed by providing a second layer metallic interconnect 12 on a first layer metallic interconnect 11, and providing via hole group 13 for coupling to a third layer metallic interconnect on an insulating film that is provided on the second layer metallic interconnect 12. As shown in FIG. 5, ends of the first layer metallic interconnect 11 are provided to overlap with the via hole group 13.
A process for manufacturing the above-described semiconductor device will be described in reference to FIGS. 6A and 6B.
A first layer metallic interconnect 11, an insulating film 22 and a second layer metallic interconnect 12 are formed on an insulating film 21. Next, a deposition of a plasma oxide film is conducted to form an interlayer insulating film 23. Next, a silica coating operation (silica coating+baking+etchback) is conducted to planarize the interlayer film 23. Deposition of a plasma oxide film is conducted again to form an insulating film 25. (FIG. 6A). Subsequently, in order to form via holes for coupling to the third layer metallic interconnect, a resist is patterned, and a wet etch process is conducted, and subsequently, a dry etch process is conducted to form via holes 13 (FIG. 6B).
While a surplus silica remained on the surface is removed via an etchback process in this occasion, a silica residue 24 remained during the silica coating process is generated, due to a presence of a step, which is created due to a presence of the first layer metallic interconnect 11. Silica remained in the step is also simultaneously etched via a wet etch process for forming vias that provides an electrical coupling between the second layer metallic interconnect and the third layer metallic interconnect, and thus hollow portions are generated. Then, insulating materials remained above these hollow portions flake off to create contaminants, leading to a reduction in the production yield.